Design a 4×4 multiplier using full adders in Verilog


The objective of this post is to implement a 4×4 multiplier using full adders in Verilog. A nxn array multiplication is simply a gathering of a 1-bit node that contains a 1-bit full adder. The node has two outputs in horizontal and vertical, and each output is passing data whether 1 or 0 to the next node horizontally and vertically. In the first row of an array multiplier, it assumes that the vertical inputs are connecting to the ground which means it passes 0 to a node. Likewise, in the first row of an array multiplier, it also assumes that the horizontal inputs are connecting to the ground, so it passes 0 to a node. In the next node that was passed data from the previous node, the horizontal output from the previous node is connecting and the horizontal input to the next node. In addition, if there is no node connected vertically, the data held in the vertical output will return as a result of a bit.

Environment, Tool, and Board

  • Ubuntu 16.04
  • Vivado 2018.3
  • Nexys A7 100T (Family: Artix-7, Package: csg324, Speed: -1L)
    • Part: xc7a100ticsg324-1L)


In the structural model of the 4×4 array multiplier using full adders in Verilog, 16 nodes should be instantiated in the module. In addition, by assigning the computed output wire after instantiating node to the output which is represented “p”, the Nexys board can physically know what to light up.

Additionally, the constraint file for the 4×4 multiplier can be found on Github designed by Digilent.


Based on the simple testbench, the binary multiplication of 1111×1111 will be 11100001. Therefore, the p[7] (led[15]), p[6] (led[14]), p[5] (led[13]), and p[0](led[8]) will be 1 (HIGH) on the simulation.


In order to compare the simulation with the result of an actual FPGA board, it tests by generating bitstream.

As observed here, when all the swt[7]~swt[0] is on, the actual result of the binary multiplication obtained the expected result.

DONE! Please let me know if you have any questions.

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